Implementation of 10TSRAM cell on comparison of power dissipation with 7TSRAM cell

Abstract

SRAM is a key component in many VLSI circuits due to their easy access. SRAM is also known as read/write memory .While read and write operations, The total power dissipation will be depends on static, dynamic and short circuit  power dissipations in SRAM cell. The basic SRAM cell is implemented with six transistors, which is high power consumed. The existing 7TSRAM cell is implemented with seven transistors, which eliminates the static power dissipation in turn off mode. Whereas, the 7TSRAM cell is suffering with short circuit power dissipation, which dominates the total power dissipation. The quantitative results shows that the total power dissipation is reduced when compared to 7TSRAM cell structure. The proposed 10T SRAM cell is simulated in cadence virtuoso software tool in 90 nm technology.