Area and Power efficient Comparator and swap switching network for Median filter

Abstract

FPGA based median filters used comparator and swap module architectures plays very important role in the field of communications and image processing. Existed conventional comparator designs are consumes large area and high computational power due to the use of compare and swap blocks in sorting networks. For this purpose, the proposed stochastic Data streaming of  Boolean computing (SDBC) technique based 8-bit comparator for sorting networks. The accuracy is increased and it consumes less number of resources. The designed comparators are useful for constructing different window sizes of bitonic sorting based median filter. By using this technique in median filter the sorting networks minimized the dynamic power. The architecture is also designed with high speed pixel streaming for data to the sorting networks without latency. Every 3X3 window consumes  a 5 clock cycles for calculating median output by using this CAS module. Experimental results shows that the designed technique produces less power and less hardware resources compared to the existed system. The design is simulated with modelsim and synthesized with Xilinx ARTIX FPGA.